This invention relates to methods of forming FLASH field effect transistor gates and non-FLASH field effect transistor gates.
In semiconductor wafer fabrication, certain integrated circuit designs form both FLASH field effect transistors and non-FLASH field effect transistors on the same semiconductor substrate. One particular aspect of doing so, and problems associated therewith, is described with reference to FIGS. 1-2.
FIG. 1 depicts a semiconductor wafer fragment 10 at one processing step. Wafer fragment 10 is comprised of a bulk monocrystalline silicon substrate 11 having first and second semiconductive material portions 12 and 13. In the context of this document, the term xe2x80x9csemiconductive substratexe2x80x9d or xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other material). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Further, in the context of this document, the term xe2x80x9clayerxe2x80x9d refers to both the singular and plural unless otherwise indicated.
A FLASH field effect transistor gate is shown as being partially formed over the first semiconductive material portion 12 of substrate 11. Such includes a first gate dielectric material 21 (i.e. silicon dioxide), a floating gate material 22 (i.e. conductively doped polysilicon) received over first gate dielectric material 21, and a partially formed second gate dielectric material 30 received over floating gate material 22. Partially formed second gate dielectric material 30 includes a first silicon dioxide layer 31 and a silicon nitride layer 32 thereover.
Referring to FIG. 2, a second silicon dioxide layer 33 is shown to have been formed over silicon nitride layer 32. Formation of second silicon dioxide layer 33 typically completes the second gate dielectric material 30, which now comprises a three layer structure which includes a first silicon dioxide layer 31, a middle silicon nitride layer 32, and a outer or second silicon dioxide layer 33. This second gate dielectric material layer 30 is commonly referred to as an xe2x80x9coxide-nitride-oxide layerxe2x80x9d, or an xe2x80x9cONO layerxe2x80x9d.
Although it is possible for the second silicon dioxide layer 33 to be deposited, under typical prior art methods it is generally formed by oxidation of silicon nitride layer 32. The prior art processing illustrated in FIG. 2 typically forms second silicon dioxide layer 33 by a thermal oxidation method which includes a long, hot, wet oxidation step. The goal of this thermal oxidation was typically to form a 15-30 xc3x85 thick silicon dioxide layer 33 on silicon nitride layer 32. By way of illustration only, example conditions to form this 15-30 xc3x85 thick silicon dioxide layer 33 included exposing semiconductor wafer fragment 10 to a temperature of about 850xc2x0 C. to about 1000xc2x0 C., and ambient pressure in the presence of steam for about 90 to 240 minutes.
Unfortunately, this thermal oxidation would also generally oxidize any exposed silicon and result in the formation of a 2000-3000 xc3x85 thick silicon dioxide layer over any such exposed silicon. For example, a 15-30 xc3x85 thick silicon dioxide layer 33 is shown to have formed on silicon nitride layer 32, while a considerably thicker silicon dioxide layer 34 is shown to have formed over the exposed silicon of second semiconductive material portion 13.
This consumption of silicon and thick oxide deposition is generally undesirable, especially when one wishes to subsequently form another integrated circuit component over silicon substrate 11, such as forming a non-FLASH field effect transistor over the second semiconductive material portion 13. Therefore, under prior art processing methods, other areas of silicon substrate 11, such as second semiconductive material portion 13, might be masked to avoid such consumption of silicon and thick oxide deposition thereover. After the thermal oxidation has been completed, the mask would be removed and a dedicated oxidation conducted to form any desired peripheral gate oxide layers over silicon substrate 11.
The invention was principally motivated by a desire to address the above-identified issue. However, the invention is in no way so limited, and is only limited by the accompanying claims as literally worded and appropriately interpreted in accordance with the Doctrine of Equivalents.
Methods of forming FLASH field effect transistor gates and a non-FLASH field effect transistor gates are described. In one implementation, a substrate comprising first and second semiconductive material portions is provided. A FLASH transistor gate is partially formed to include at least a first gate dielectric material received over the first semiconductive material portion, a floating gate material overlying the first gate dielectric material, and a second gate dielectric material received over the floating gate material. The second gate dielectric material comprises silicon nitride. In a common oxidizing step, the silicon nitride of the second gate dielectric material and the second semiconductive material portion are oxidized effective to form both a) a gate oxide layer of a non-FLASH transistor gate overlying the second semiconductive material portion, and b) silicon dioxide as part of the second gate dielectric material of the FLASH transistor gate. In one implementation, in a common oxidizing step, the silicon nitride of the second gate dielectric material and the second semiconductive material portion are exposed to atomic oxygen under conditions effective to form both a) a gate oxide layer of a non-FLASH transistor gate overlying the second semiconductive material portion, and b) silicon dioxide as part of the second gate dielectric material of the FLASH transistor gate. Additional implementations are contemplated.